As industry is moving toward high-speed input/output (I/O) of 5 gigatransfers per second (GT/s) and higher, low jitter clocking architectures have become a more popular building block in phase locked loop (PLL) design. Compared with a self-biased differential ring oscillator based voltage-controlled oscillator (VCO), an inductor-capacitor VCO (designated as LC-VCO) may have a number of advantages. For instance, an LC-VCO may have lower random jitter at lower power consumption, as compared to ring oscillator based VCO designs. In addition, full-loop simulation also shows that a PLL implemented with an LC-VCO (designated as LC-PLL) may have better power supply rejection ratio (PSRR) than PLLs implemented with ring oscillator based VCO designs. There remain, however, a number of non-trivial issues associated with LC-PLL to be resolved.